
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
IDT / ICS 3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER
14
ICS84314AY-02 REV. A MARCH 24, 2009
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 6A and 6B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 6A. 3.3V LVPECL Output Termination
Figure 6B. 3.3V LVPECL Output Termination
V
CC - 2V
50
50
RTT
Z
o = 50
Z
o = 50
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50
Z
o = 50
FOUT
FIN